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? semiconductor MSM7582/7582b 1/24 ? semiconductor MSM7582/7582b p /4 shift qpsk modem general description the MSM7582/7582b are cmos ics for the p /4 shift qpsk modem developed for the digital cordless telephone systems. the devices are designed for personal and cell station applications, the MSM7582b is the improved MSM7582 in modulator burst rise-up and fall-down characteristics. features ? ? ? ? ? single power supply (v dd : 2.7 v to 3.6 v) (modulator block) ? ? ? ? ? built-in root nyquist filter for baseband limiting (50% roll-off) ? ? ? ? ? ramp bit for burst signal rise-up: MSM7582/1.75 symbols MSM7582b/2.0 symbols ? ? ? ? ? ramp bit for burst signal fall-down: MSM7582/2.75 symbols MSM7582b/2.0 symbols ? ? ? ? ? built-in d/a converters for analog output of quadrature signal i/q components and power envelope output i 2 + q 2 ? ? ? ? ? differential i/q analog output format ? ? ? ? ? i/q output dc offset / gain adjustable (demodulator block) ? ? ? ? ? full digital system, p /4 shift qpsk demodulation ? ? ? ? ? input if signal frequency selectable: 1.2/10.7/10.75/10.8 mhz ? ? ? ? ? built-in clock recovery: 4 circuits useful for cell station (common) ? ? ? ? ? various power-down modes: tramsmit/receive independant ? ? ? ? ? built-in precise analog voltage reference ? ? ? ? ? mcu serial interface for mode setting and built-in test circuit ? ? ? ? ? test modes: eye pattern / afc compensating signal / phase detection signal, possible to monitor ? ? ? ? ? transmission speed: 384 kbps ? ? ? ? ? low power consumption operating mode : 15 ma typ. / modulator (v dd = 3.0 v) : 9 ma typ. / demodulator (v dd = 3.0 v) whole system power-down mode: 0.01 ma typ. (v dd = 3.0 v) ? ? ? ? ? package: 32-pin plastic tsop (tsopi32-p-814-0.50-1k)(product name : MSM7582ts-k) (product name : MSM7582bts-k) e2u0035-16-x2 this version: jan. 1998 previous version: nov. 1996
? semiconductor MSM7582/7582b 2/24 block diagram ifin agnd dgnd v dd phase detector delay detector ifck mck x1 den exck din dout s e l x2 control register (cr) to each block pdn0 pdn1 pdn2 afc dpll decision unit rxc rxd s e l sls1 sls2 + 1 - 1 + 1 - 1 + 1 i+ iC q+ qC env root nyquist lpf s e l s/p mapping s e l apll txd txw txci 1/10 txco sg to internal sg to each block ifsel0 (from cr) ifsel1 (from cr) sl4 sl3 sl2 sl1 to monitor output of each block to modem env ps/cs rpr rcw afc test1, test0 (from cr) to monitor output of each block txcsel (from cr) 3.84 mhz 384 khz decoder env d/a conv vref i d/a conv q d/a conv to d/a
? semiconductor MSM7582/7582b 3/24 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 agnd sg i+ iC q+ qC env pdn0 pdn1 pdn2 v dd sls1 sls2 rcw afc rpr dgnd ifin txci txco txd txw den exck din dout mck rxd rxc ifck x2 x1 32-pin plastic tsop
? semiconductor MSM7582/7582b 4/24 pin and functional descriptions txd transmit data input for 384 kbps. txci transmit clock input. when the control register cr0 C b6 is 0, a 384 khz clock pulse synchronous with txd should be input to this pin. this clock pulse should be continuous because these devices use apll to generate the internal clock pulse. when cr0 C b6 is 1, a 3.84 mhz clock pulse should be input to this pin. when the 3.84 mhz clock pulse is applied, txco outputs a 384 khz clock pulse, which is generated by dividing the 3.84 mhz to txci by 10. the transmit data, synchronous 384 khz clock pulse, should be input to the txd. in this case the devices do not use apll, and the 3.84 mhz clock pulse need not be continuous. (refer to fig. 1.) txco transmit clock output. when cr0 - b6 is 0, txco outputs the 384 khz clock pulse (apll output) for monitoring purposes. when cr0 C b6 is 1, this pin outputs a 384 khz clock pulse generated by dividing the txci input by 10. (refer to fig. 1.) when cr0 C b6 = 0 and cr5 C b7 = 1, this pin outputs the burst timing position. txw transmit data window input. the transmit timing signal for the burst data is input to the device pin. if txw is 1, the modulation data is output. however, the MSM7582 is different from the MSM7582b in the ramp response time for burst rise-up and burst fall-down of i, q modulated outputs, as shown in the table below. (refer to fig, 1-1 for the MSM7582 and fig, 1-2 for the MSM7582b) MSM7582 MSM7582b ramp rise-up 1.75 symbols 2 symbols ramp fall-down 2.75 symbols 2 symbols the txco burst position output timing discribed before, is different, according to this table.
? semiconductor MSM7582/7582b 5/24 MSM7582 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 dn-1 dn txd txci (384 khz) txw txco (384 khz) i, q ramp rise-up 1.75 symbols delay of 6.25 symbols ramp fall-down 2.75 symbols delay of 6.25 symbols (1) cr0 e b6 = "0" d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 dn-1 dn txd txci (3.84 mhz) txw txco (384 khz) i, q ramp rise-up 1.75 symbols delay of 6.25 symbols ramp fall-down 2.75 symbols delay of 6.25 symbols (2) cr0 e b6 = "1" figure 1-1 transmit timing diagram
? semiconductor MSM7582/7582b 6/24 MSM7582b d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 dn-1 dn txd txci (384 khz) txw txco (384 khz) i, q ramp rise-up 2 symbols delay of 6.25 symbols ramp fall-down 2 symbols delay of 6.25 symbols (1) cr0 e b6 = "0" d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 dn-1 dn txd txci (3.84 mhz) txw txco (384 khz) i, q ramp rise-up 2 symbols delay of 6.25 symbols ramp fall-down 2 symbols delay of 6.25 symbols (2) cr0 e b6 = "1" figure 1-2 transmit timing diagram i+, iC quadrature modulation signal i component differential analog outputs. their output levels are 500 mv pp with 1.6 vdc as the center value. the output pin load conditions are: r 3 10 k w , c 20 pf. the gain of these pins can be adjusted using the control register cr1 C b7 to b4, and the offset voltage at the iC pin can be adjusted using cr3 C b7 to b3. q+, qC quadrature modulation signal q component differential analog outputs. their output levels are 500 mv pp with 1.6 vdc as the center value. the output pin load conditions are: r 3 10 k w , c 20 pf. the gain of these pins can be adjusted using the control register cr1 C b3 to b0, and the offset voltage at the qC pin can be adjusted by using cr4 C b7 to b3.
? semiconductor MSM7582/7582b 7/24 env quadrature modulation signal envelope ( i 2 + q 2 )output. its output level is 500 mv pp with 1.6 vdc as a center value. the output pin load conditions are : r 3 10 k w , c 20 pf. the gain of this output can be adjusted using the control register cr2 C b7 to b4. this pin is also used to monitor eye pattern, afc compensating signal, and phase defection of the demodulator block during the test mode. refer to the description of the control register for details. sg internal reference voltage output. the output voltage is about 2.0 v. a bypass capacitor should be connected between this pin and the agnd pin. pdn0, pdn1, pdn2 inputs for power-down control. pdn0 controls the standby / communication modes, pdn1 controls the modulator, and pdn2 controls the demodulator. refer to table 1 for details. table-1 power down control pdn0 standby mode communication mode pdn2 pdn1 0 0/1 1 010 100 101 110 111 function all power-down. the control register is reset. modulator power is off (vref and pll power are also off). demodulator power is on. modulator power is off (vref and pll power is on). i and q outputs are in a high-impedance state. only demodulator clock recovery block power is on. modulator power is on only demodulator clock recovery block power is on. modulator power is off (vref and pll power is on). i and q outputs are in a high-impedance state. demodulator power is on. demodulator power is on. modulator power is on mode mode a mode c mode d mode e mode f mode g 000 all power-down. the control register is not reset. mode b v dd +3 v power supply voltage. agnd analog signal ground. dgnd digital signal ground. agnd and dgnd are not connected in the device. this pin should be tied to the agnd pin on the pcb as close as possible from the device.
? semiconductor MSM7582/7582b 8/24 mck master clock input. the clock frequency is 19.2 mhz. ifin modulated signal input for the demodulator block. select the if frequency from 1.2 mhz, 10.7 mhz, 10.75 mhz, and 10.8 mhz, based on cr0 C b4 and b3. ifck clock signal input for demodulator block if frequencies (10.7 mhz or 10.75 mhz). if the if frequency is 10.7 mhz, 19.0222 mhz should be supplied. when it is 10.75 mhz, 19.1111 mhz should be supplied. when the if frequency is 1.2 mhz or 10.8 mhz, set this pin to 0 or 1. (refer to fig. 2.) x1, x2 crystal oscillator connection pins. when supplying a 19.0222 mhz or 19.1111 mhz clock to ifck, use these pins (refer to fig. 2.) x1 ifck 19.0222 mhz or 19.1111 mhz when ifin = 10.7 mhz or 10.75 mhz x2 MSM7582/7582b x1 ifck x2 MSM7582/7582b when ifin = 1.2 mhz or 10.8 mhz figure 2 how to use ifck, x1, and x2 rxd, rxc receive data and clock output. when power is turned on, the outputs of circuits selected by sls1 and sls2 appear at these pins. (refer to fig. 3) rxd1 rxc sls2 the recovery data and clock pulse are selected asynchronously using the sls signals. sls1 figure 3 rxd and rxc timing diagram
? semiconductor MSM7582/7582b 9/24 sls2, sls1 receiver slot select signal inputs. the devices have four sets of clock recovery circuit to each channel and four afc information storage registers. one these circuits is selected from a combination of the signals at these pins. (sls2, sls1) = (0, 0): slot 1, (0, 1): slot 2 (1, 0): slot 3, (1, 1): slot 4 rpr high-speed phase clock control signal input for the clock recovery circuit. if this pin is 1, the clock recovery circuit starts in the high-speed phase clock mode. when the phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically. when this pin is 0, the circuit is always in the low-speed phase clock mode. afc afc operation range specification signal input. as shown in fig. 4, the afc information is reset when both afc and rpr are set to 1. afc operation starts after a fixed number of clock cycles and after the afc information is reset. if rpr is set to 1, an average number of times that afc turns on is low. if rpr is 0, afc is high. if afc is 0, frequency error is not calculated, but the frequency is corrected using an error that is held. rcw clock recovery circuit operation on/off control signal input. if rcw pin is 0, dpll does not make any phase corrections. afc afc information is reset. rpr average number of times afc is low. afc information is maintained. afc rpr afc information is maintained. the clock recovery circuit starts with the previous afc information. "0" (case1) (case2) average number of times afc is high. average number of times afc is high. figure 4 afc control timing diagram
? semiconductor MSM7582/7582b 10/24 den , exck, din, dout serial control ports for the microprocessor interface. the MSM7582 and MSM7582b contain a 6-byte control register. an external cpu uses these pins to read data from and write data to the control register. den is an enable signal input pin. exck is a data shift clock pulse input pin. din is an address and data input pin. dout is a data output pin. figure 5 shows an input/output timing diagram. high impedance high impedance (a) data write timing diagram (b) data read timing diagram den w exck din a2 dout a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 r a2a1a0 b7 b6 b5 b4 b3 b2 b1 b0 den exck din dout figure 5 mcu interface input/output timing diagram
? semiconductor MSM7582/7582b 11/24 the register map is shown below table-2 control register map register address a2 a1 a0 data r/w b7 b6 b5 b4 b3 b2 b1 b0 cr0 cr1 cr2 cr3 cr4 cr5 000 001 010 011 100 101 r/w r/w r/w r/w r/w r/w ps/cs txcsel modoff ifsel1 ifsel0 envsel test1 test0 env gain3 env gain2 env gain1 env gain0 bsto enbl ict6 ict5 ict4 local inv1 local inv0 clk sel1 clk sel0 ich gain3 ich gain2 ich gain1 ich gain0 qch gain3 qch gain2 qch gain1 qch gain0 ich offset3 ich offset2 ich offset1 ich offset0 ich offset4 qch offset3 qch offset2 qch offset1 qch offset0 qch offset4 r/w : read/write enable r : read-only register
? semiconductor MSM7582/7582b 12/24 absolute maximum ratings parameter power supply voltage digital input voltage operating temperature storage temperature symbol v dd v din t op t stg condtion rating 0 to 5 C0.3 to v dd +0.3 C25 to +70 C55 to +150 unit v v c c recommended operating conditions parameter symbol condtion min. typ. max. unit power supply voltage v dd 2.7 3.6 v input high voltage v ih v dd v input low voltage v il 0 v master clock frequency f mck mhz clock duty cycle d cck mck, ifck, txci 40 50 60 % if input duty cycle d cif ifck 45 50 55 % 19.2 f txc2 mhz 3.84 txci (when cr0 C b6 = "1") mck 0.45 v dd 0.16 v dd operating temperature range ta C25 +70 c all digital input pins all digital input pins f txc1 khz 384 txci (when cr0 C b6 = "0") modulator input frequency f ifck2 mhz C 50 ppm 19.1111 + 50 ppm ifck (when ifin = 10.75 mhz) f ifck1 mhz C 50 ppm 19.0222 + 50 ppm ifck (when ifin = 10.7 mhz) demodulator input frequency (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) electrical characteristics dc characteristics parameter power supply current output high voltage output low voltage input leakage current symbol i dd1 i dd2 i ih i il condition mode a, mode b (when v dd = 3.0 v) i oh = 0.4 ma i ol = C1.2 ma min. 0.5 v dd 0.0 typ. 0.02 5.5 max. 0.05 11.0 10 10 v dd 0.4 unit ma ma m a m a v v (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) v oh v ol i dd3 i dd4 mode c (when v dd = 3.0 v) mode d (when v dd = 3.0 v) 5.5 11.5 11.0 23.0 ma ma i dd5 i dd6 mode e (when v dd = 3.0 v) mode f (when v dd = 3.0 v) 9.5 14.0 19.0 28.0 ma ma mode g (when v dd = 3.0 v)
? semiconductor MSM7582/7582b 13/24 parameter output resistance load output capacitance load output dc voltage level output ac voltage level symbol r liq c liq v dc1 v ac condtion min. 1.0 1.55 typ. 1.6 360 max. 20 unit k w pf v mv pp i+, iC, q+, qC, env i+, iC, q+, qC, env i+, iC, q+, qC (txw = 0) i+, iC, q+, qC (txd = 0) (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) v dc2 1.77 v i+ (cr0 C b5 = 1) when not modulated v dc3 1.67 v q+ (cr0 C b5 = 1) when not modulated v dc4 1.35 v env (txw = 0) v dc5 1.72 v env (txw = 1, cr0 C b2 = 0, txd = 0) v dc6 1.63 v env (txw = 1, cr0 C b2 = 1, txd = 0) output dc voltage adjustment level range dcvl 45 mv output ac voltage adjustment level range acvl 4 % out-of-band spectrum p600 60 db 600 khz detuning (*) p900 65 db 900 khz detuning (*) modulation accuracy evm 1.0 3.0 % rms demodulator if input level ifv 0.5 v dd v pp ifin input level ifin input impedance rif 20k w cif 5 pf sg output voltage vsg 2.0 v sg output impedance rsg 1.5 k w 1.65 analog interface characteristics * power attenuation at 600 khz or 900 khz 96 khz as referred to two times of the power in frequency band of 0 to 96 khz
? semiconductor MSM7582/7582b 14/24 digital interface characteristics transmitter digital input/output setting time t sx C200 200 t ds 0 200 t xd1 0 200 ns t xd3 0 200 parameter symbol min. typ. max. unit (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) other condtion c load = 50 pf fig. 6 ns ns ns t dh t xd2 t xd4 t m1 50 ns t m2 50 ns t m3 50 ns t m4 50 ns t m5 100 ns t m6 50 ns t m7 50 ns t m8 0 100 ns t m9 50 ns t m10 50 ns t m11 0 50 ns serial port digital input/output setting time c load = 50 pf fig. 8 f exck 10mhz exck exck clock frequency t rd1 t rd2 t rs1 to t rw t rs4 receiver digital input/output setting time c load = 50 pf fig. 7 0 200 ns 0 200 ns 10 m s 10 m s
? semiconductor MSM7582/7582b 15/24 timing diagram 1 2 3 n-2 n-1 n n+1 t ds t sx txci [txco*] (384 khz) txw txd t dh 123 n-2 n-1 n t sx txci (3.84 mhz) 1 2345678910 t xd1 t xd2 t xd1 txco (384 khz) transmit data input timing transmit clock (txco) output timing (when cr0 C b6 = 1) txci (384 khz) 1 289n n+1 n+17 t xd3 txco transmit burst position output (txco) timing (when cr0 C b6 = 0 and cr5 C b7 = 1) txw n+18 n+19 t xd4 m7582 txci (384 khz) 1 289n n+1 n+17 t xd3 txco txw n+18 n+19 t xd4 m7582b * [ ]: when cr0 C b6 = "1", txco is indicated. figure 6 transmit (modulator) digital input/output timing
? semiconductor MSM7582/7582b 16/24 rxc afc rxd t rd1 t rs4 t rs3 t rd2 rpr t rw rcw t rs2 t rs1 sls1 sls2 figure 7 receiver (demodulator) digital input/output timing t m1 t m3 t m4 t m2 123456 t m6 t m7 t m5 11 12 t m10 t m11 w/r a2 a1 a0 b7 b7 t m8 b1 b0 b1 b0 t m4 den exck din dout figure 8 serial control port interface
? semiconductor MSM7582/7582b 17/24 functional description control registers (1) cr0 (basic operation mode setting) b7 b6 b5 b4 b3 b2 b1 b0 ps/cs txc sel mod off ifsel 1 ifsel 0 env sel test 1 test 0 00000000 initial value (*) cr0 * the initial value is set when a reset signal is supplied by a pdn. b7: ps/cs selection 1/cs (4 clock recovery dplls are on.) 0/ps (2 clock recovery dplls are on.) b6: transmit timing clock selection 0/txci input: 384 khz. txco output: 384 khz output from apll. transmit data txd is input in synchronization with the rising edge of txci (apll is on.) 1/txci input: 3.84 mhz. txco output: 384 khz (one-tenth of the txci frequency). transmit data txd is input in synchronization with the rising edge of txco (apll is off.) b5: modulation on/off control 1/modulation off (with phase fixed) 0/modulation on. b4, b3: receiver input if frequency selection (0, 0), (0, 1): 1.2 mhz (1, 0): 10.8 mhz (1, 1): 10.7 mhz/10.75 mhz b2: transmit envelope (i 2 + q 2 or i 2 + q 2 )output selection 1/i 2 + q 2 output 0/ i 2 + q 2 output b1, b0: test mode selection bits. each monitor output is output to the transmit env pin. (0, 0): transmit envelope (i 2 + q 2 or i 2 + q 2 ) output (0, 1): receiver phase detection signal output (1, 0): receiver delay detection signal output (1, 1): receiver afc information output
? semiconductor MSM7582/7582b 18/24 (2) cr1 (i, q gain adjustment) b7 b6 b5 b4 b3 b2 b1 b0 ich gain3 ich gain2 ich gain1 ich gain0 qch gain3 qch gain2 qch gain1 qch gain0 00000000 initial value cr1 b7 to b4: i+/iC output gain setting, in 3 mv steps (refer to table-3.) b3 to b0: q+/qC output gain setting, in 3 mv steps (refer to table-3.) (3) cr2 (env gain adjustment) b7 b6 b5 b4 b3 b2 b1 b0 env gain3 env gain2 env gain1 env gain0 00000000 initial value cr2 b7 to b4: env output gain adjustment (refer to table-3.) b3 to b0: not used table-3 i, q, and env output gain values cr1-b7 -b6 -b5 -b4 cr1-b3 -b2 -b1 -b0 cr2-b7 -b6 -b5 -b4 0 111 0 110 0 101 0 100 0 011 0 010 0 001 0 000 1 111 1 110 1 101 1 100 1 011 1 010 1 001 1 000 amplitude 1.042 1.036 1.030 1.024 1.018 1.012 1.006 1.000 0.994 0.988 0.982 0.976 0.970 0.964 0.958 0.952 reference value (reference value) description
? semiconductor MSM7582/7582b 19/24 (4) cr3 (iC output offset voltage adjustment) b7 b6 b5 b4 b3 b2 b1 b0 ich offset4 ich offset3 ich offset2 ich offset1 ich offset0 00000000 initial value cr3 b7 to b3: iC output pin offset voltage adjustment (refer to table-4.) b2 to b0: not used (5) cr4 (qC output offset voltage adjustment) b7 b6 b5 b4 b3 b2 b1 b0 qch offset4 qch offset3 qch offset2 qch offset1 qch offset0 00000000 initial value cr4 b7 to b4: qC output pin offset voltage adjustment (refer to table-4.) b3 to b0: not used table-4 i and q channel offset adjustment values description 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 cr4-b7 b6 b5 b4 b3 +45 +42 +39 +36 +33 +30 +27 +24 +21 +18 +15 +12 +9 +6 +3 0 description 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 cr4-b7 b6 b5 b4 b3 C3 C6 C9 C12 C15 C18 C21 C24 C27 C30 C33 C36 C39 C42 C45 C48 cr3-b7 b6 b5 b4 b3 cr3-b7 b6 b5 b4 b3 mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv offset offset
? semiconductor MSM7582/7582b 20/24 (6) cr5 b7 b6 b5 b4 b3 b2 b1 b0 bsto enbl ict6 ict5 ict4 local inv1 local inv0 clk sel1 clk sel0 00000000 initial value cr5 b7: modulator burst window output enable bit. 1/the timing of the i and q baseband modulation output burst is output at the txco pin. 0/the 384 khz transmit timing clock pulse is output at the txco pin. b6 to b4: ict6 to ict4. device test control bits. b3, b2: local inverting mode setting bits. (1, 1) = local inverting mode (0, 0) = normal mode b1: clock pulse shaping mode selection bit. 1/clock pulse shaping mode (refer to fig 9.) 0/oscillator circuit mode b0: power-on control bit for x1, x2 pins, when the clock pulse shaping mode. 1/ always power-on 0/ power-down in the whole device power-down state when power on otherwise. note: cr5 C b6 to b4 are used to test the device. they should be set to 0 during normal operation. x1 mck x2 MSM7582/82b ts-k tcxo 19.2 mhz about 0.7 to 1.0 v pp pulse shape within about 3 v pp to other input of 19.2 mhz figure 9 example of application circuit when the clock pulse shaping mode is generated by cr5-b1
? semiconductor MSM7582/7582b 21/24 mode e mode b mode d mode g mode c mode f pdn1 = 0 pdn2 = 0 pdn1 = 0 pdn2 = 1 pdn1 = 0 pdn2 = 1 pdn1 = 0 pdn2 = 0 pdn1 = 1 pdn2 = 1 pdn1 = 1 pdn2 = 0 1 ms 5 m s 40 m s 40 m s 5 m s 5 ms standby mode (pdn0 = 0) communication mode (pdn0 = 1) note: the transition time is 1 m s or less unless otherwise stated mode a pdn1 = 1 state transition time figure 10 power-down state transition time
? semiconductor MSM7582/7582b 22/24 figure 11 example of circuit configuration application circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 agnd sg i+ iC q+ qC env pdn0 pdn1 pdn2 v dd sls1 sls2 rcw afc rpr dgnd ifin txci txco txd txw den exck din dout mck rxd rxc ifck x2 x1 MSM7582ts-k c3 c2 c1 v dd modulator i component output power-down control signal demodulator control signal demodulator if input modulator 384 khz input modulator input data modulator data window receive clock output receive data output 19.2 mhz input control register control signal c4 c1 = 10 m f c2 = c3 = 0.1 m f c4 = 1000 pf + to orthogonal modulator modulator q component output
? semiconductor MSM7582/7582b 23/24 demodulator control timing diagram (example) democulator unit modulator input data pdn2 sls2 240 bits 625 m s r1 g slot 1 r2 g slot 2 r3 g slot 3 r4 g slot 4 g sls1 "0" "0" "0" "1" "1" "0" "1" "1" afc r1 r2 rxd r3 r4 rxc timing for cs g g g g g g g g r r r r ss ss pr pr uw pr cr cr g g g g g g g g rxd afc rpr rcw 56 bits 64 bits g g g g g g g g r r r r ss ss pr pr uw pr cr cr g g g g g g g g rxd 8 bits rpr rcw "0" when the strength of the received wave is small. less than 30 bits afc g r ss pr uw cr : : : : : : guard bit ramp bit start symbol bit preamble bit unique word bit crc bit for ps, the window is initially open to wait for the control signal from cs. rpr is closed after uw is detected. pdn2 sls2 sls1 "0" "0" afc r1 rxd rxc timing for ps rpr rcw afc (1) control channel / synchronous burst (ss + pr = 64 bits) (3) communication channel (ss + pr = 8 bits) when the strength of the received wave is large (2) when synchronization is not established (for ps only)
? semiconductor MSM7582/7582b 24/24 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tsop i 32-p-814-0.50-1k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.27 typ. mirror finish

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